Characterization in Silicon Processing by Yale Strausser

By Yale Strausser

This booklet stories options in which silicon processing engineers operating with semiconductors can meet the calls for for greater fabric caliber and function made worthwhile through more and more stringent necessities, reminiscent of lowering barrier movie thicknesses. one of the innovations defined are tracking the effectiveness of floor cleansing strategies; settling on the volume of silicon intake in the course of barrier movie and silicide development; and silicon selective epitaxial development.

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134. 21 D. J. Ruprecht, L. G. Hellwig, and J. A. Rossi. In Semiconductor Fabrication: Technology and Metrology, ASTM STP 990. (D. C. ) American Society for Testing and Materials, Philadelphia, 1989, p. 87. 22 E Secco d'Aragona. / Electrochem. Soc. 119, 948, 1972 23 M. W. Jenkins. /. Electrochem. Soc. 124, 758, 1977. 24 D. G. Schimmel. /. Electrochem. Soc. 126, 479, 1979. " Annual Book of ASTM Standards. F 80-88a. American Society for Testing and Materials, Philadelphia, 1988. 26 K. V. Ravi. Imperfections and Impurities in Semiconductor Silicon.

Etching of the substrate during precleaning can remove a substantial fraction of such a diffusion and greatly increase the diffusion sheet resistance. Hence, such etching cannot be tolerated in these technologies. Consequently, precleaning practice today commonly uses a high-temperature bake in hydrogen, rather than an etch, to clean the surface. The effect of high-temperature bakes on surface cleanliness has been the subject of a number of studies. Auger spectroscopy, ellipsometry, and RHEED were used to study the removal of oxygen- and carbon-containing species in a special reactor design which allowed transfer from a growth chamber to an analysis chamber.

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